1. Field of the Invention
The present invention relates to an interconnection area decision processor. More specifically, it relates to an interconnection area decision processor which decides vertical widths of interconnection areas in a gate array where rows of transistors are arranged with minimal spaces and any portion of the LSI chip can be used for constructing logic elements with the remaining areas being used for interconnections.
2. Description of the Prior Art
FIG. 1 illustrates data on channel vertical widths to which the present invention is applied and which are processed by a conventional automatic interconnection processor,
FIG. 2 illustrates data on arrangement of cells,
FIG. 3 shows exemplary LSI chip structure processed by the conventional automatic interconnection processor,
FIG. 4 shows an example of channel interconnection and
FIG. 5 schematically shows the structure of the conventional automatic interconnection processor.
With reference to FIGS. 1 to 5, description is now made on a conventional automatic routing method. Referring to FIG. 3, cells 31 each forming the element in logic design and layout design with a certain logical function are arranged in horizontal rows on a large-scale integrated circuit chip. Input/output buffer cells 32 are arranged around the cells 31 and interconnection areas (hereinafter referred to as channels) 33 are defined between adjacent rows of the cells 31. The channels 33 are identical in horizontal width to each other except for vertical channels, while the same may be different in vertical width from each other. The horizontal and vertical widths of each channel 33 are decided by hand without consideration of the degree of interconnection congestion in advance to automatic placement/routing.
In general, the cells 31 and the input/output buffer cells 32 are automatically interconnected in the following manner: First loose interconnection paths through the channels 33 are decided. Then the respective channels 33 are entirely interconnected along certain sequence. Detailed interconnection paths within the respective channels 33 are decided per channel, thereby to complete the entire interconnection.
FIG. 4 shows an example of interconnection with respect to a single channel 33, while this figure may be rotated by 90.degree. with respect to a vertical channel. Cell terminals 33a for fixing positions are disposed on upper and lower edges of the channel 33, while left and right edges thereof, which are generally bounded by other channels 33, are provided with terminals 33b whose positions are not decided. A set of the terminals 33a and 33b to be equipotentially connected is called as a signal net. In the channel 33, two layers which are isolated through an interlayer insulating film are available for interconnection, that is, the first layer is used for a horizontal interconnection segment 33c and the second layer is used for a vertical interconnection segment 33f. The interconnection segments on the different layers in the same signal net are connected by a via hole 33d provided in the interlayer insulating film. The horizontal interconnection segment 33c is placed on a horizontal interconnection grid line 33e called a track and the vertical interconnection segment 33f is placed on a vertical interconnection grid line (not shown).
With reference to FIG. 5, description is now made on the conventional automatic interconnection processor. A memory device 11 stores data on cell arrangement as shown in FIG. 2, while another memory device 14 stores data (the number of tracks) on the vertical widths of respective channels as shown in FIG. 1. A computer 15 performs interconnection processing on the basis of the data on cell arrangement and the data on the vertical widths of the respective channels stored in the memory devices 11 and 14 respectively. A memory device 16 stores data indicating the result of interconnection processed by the computer 15.
In the conventional routing method as hereinabove described, the number of tracks of the channels are previously decided by hand and cannot be decided according to the degree of interconnection congestion of each channel. Thus, increase in circuit scale easily leads to unroutable signal net caused by interconnection congestion, while the density of integration of the elements cannot be improved since the vertical width of a channel cannot be adjusted according to interconnection congestion.